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MA2909/11
APRIL 1995
DS3577-3.4
PRELIMINARY INFORMATION
MA2909/11
RADIATION HARD MICROPROGRAM SEQUENCER
The MA2909/11 Microprogram Sequencer is fully compatible with the industry standard 2909A and 2911A components, and forms part of the GPS 2900 Series of devices. The series offers a building block approach to microcomputer and controller design, with each device in the range being expandable to permit efficient emulation of any microcode machine. The devices have tristate outputs and have an internal address register, with all internal registers changing state on LOW to HIGH clock transition. The 4-bit slice can cascade to any number of microwords. Branch input for N-way branches is supported. Additional features include: I 4-bit cascadable microprogram counter. I 4 x 4 file with stack counter supporting nesting microsubroutines. I Zero input for returning to the zero microcode word. I Individual OR input for each bit for branching to higher microinstructions (2909 only). The 2909 is a 4-bit wide address controller intended for sequencing through a series of microinstructions contained in a ROM or PROM. Two 2909s may be interconnected to generate an 8-bit address (256 words), and three may be used to generate a 12-bit address (4K words). The 2909 can select an address from any of four sources: 1) A set of external direct inputs (D); 2) External data from the R inputs, stored in an internal register; 3) A four-word push/pop stack; or 4) A program counter register (which usually contains the last address plus one). The push/pop stack includes certain control lines so that it can efficiently execute nested subroutine linkages. Each of the four outputs can be OR'ed with an external input for conditional skip or branch instructions, and a separate line forces the outputs to all zeroes. The outputs are three-state. The 2911 is an identical circuit to the 2909 except the four OR inputs are removed and the D and R inputs are tied together.
FEATURES
I Fully Compatible with Industry Standard 2909A and 2911A Components I Radiation Hard CMOS SOS Technology I High SEU Immunity I High Speed / Low Power I Fully TTL Compatible
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MA2909/11
STK PTR
Figure 1: Microprogram Sequencer Block Diagram
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MA2909/11
The 2909/2911 are CMOS SOS microprogram sequencers intended for use in high-speed microprocessor applications. The device is a cascadable 4-bit slice such that two devices allow addressing of up to 256 words of microprogram and three devices allow addressing of up to 4K words of microprogram. A detailed logic diagram is shown in figure 1. The device contains a four input multiplexer that is used to select either the address register, direct inputs, microprogram counter, or file as the source of the next microinstruction address. This multiplexer is controlled by the S0 and S1 inputs. The address register consists of four D-type, edge triggered flip-flops with a common clock enable. When the address register enable is LOW, new data is entered into the register on the clock LOW-to-HlGH transition. The address register is available at the multiplexer as a source for the next microinstruction address The direct input is a 4-bit field of inputs to the multiplexer and can be selected as the next microinstruction address. On the 2911 the direct inputs are also used as inputs to the register. This allows an N-way branch where N is any word in the microcode. The 2909/2911 contains a microprogram counter (PC) that is composed of a 4-bit incrementer followed by a 4bit register. The incrementer has carry-in (Cn) and carry-out (Cn + 4) such that cascading to larger word lengths is straight forward. The PC can be used in either of two ways. When the least significant carry-in to the incrementer is HIGH, the microprogram register is loaded on the next clock cycle with the current Y output word plus one (Y + 1 PC). Thus sequential microinstructions can be executed. If this least significant Cn is LOW, the incrementer passes the Y output word unmodified and the microprgram register is loaded with the same Y word on the next clock cycle (Y PC). Thus, the same microinstruction can be executed any number of times by using the 4x4 file (stack). The file is used to provide return address linkage when executing microsubroutines. The file contains a built-in stack pointer (SP) which always points to the last file word written. This allows stack reference operations (looping) to be performed without a push or pop. The stack pointer operates as an up/down counter with separate push/pop and file enable inputs. When the file enable input is LOW and the push/pop input is HIGH, the PUSH operation is enabled. This causes the stack pointer to increment and the file to be written with the required return linkage - the next microinstruction address following the subroutine jump which initiated the PUSH. If the file enable input is LOW and the push/pop control is LOW, a POP operation occurs. This implies the usage of the return linkage during this cycle and thus a return from subroutine. The next LOW-to-HlGH clock transition causes the stack pointer to decrement. If the file enable is HIGH, no action is taken by the stack pointer regardless of any other input. The stack pointer linkage is such that any combination of push, pop or stack references can be achieved. One microinstruction subroutine can be performed. Since the stack is 4 words deep, up to four microsubroutines can be nested. The ZERO input is used to force the four outputs to the binary zero state. When the ZERO input is LOW all Y outputs are LOW regardless of any other inputs (except OE). Each Y output bit also has a separate OR input such that a conditional logic one can be forced at each Y output. This allows jumping to different microinstructions on programmed conditions. The 2909/2911 feature three-state Y outputs. These can be particularly useful in designs requiring external equipment to provide automatic checkout of the microprocessor. The internal control can be placed in the high impedance state and preprogrammed.
MULTIPLEXER SELECT CODES
Table 1 lists the select codes for the multiplexer. The two bits applied from the microword register (and additional combinational logic for branching) determine which data source contains the address for the next microinstruction. The contents of the selected source will appear on the Y outputs. Table 1 also shows the truth table for the output control and for the control of the push/pop stack. Table 2 shows in detail the effect of S 0, S1, FE and PUP on the 2909. These four signals define the address that apears on the Y outputs and what the state of all the internal registers will be following the clock LOW-to-HlGH edge. In this illustration, the microprogram counter is assumed to contain initially some word J, the address register some word K, and the four words in the push/ pop stack contain Ra through Rd. OR1 X X H L ZERO X L H H OE H L L L Y1 Z L H Source selected by S0S1
H = High, L = Low, Z = High Impedance Table 1a: Output Control
FE H L
ZERO X H
PUSH-POP stack change No change Increment stack pointer, then push current PC on to STK0 Pop stack (decrement stack pointer)
L L H = High, L = Low, X = Irrelevant
Table 1b: Synchronous Stack Control
S1 S2 L L H H L H L H
Source for Y outputs Microprogram counter Address/Holding register Push-Pop stack Direct inputs Table 1c: Address Selection
Symbol PC AR STKO D1
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MA2909/11
Cycle N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 S1 L L L L L L H H H H H H S0 L L L H H H L L L H H H H X L H L L H X L H L L H X L H L L H X L H FE L PUP L PC J J+1 J J+1 J J+1 J K+1 J K+1 J K+1 J Ra + 1 J Ra + 1 J Ra + 1 J D+1 J D+1 J D+1 REG STK0 STK1 STK2 STK3 YOUT K K K K K K K K K K K K K K K K K K K K K K K K Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Ra Rb Ra J Ra Ra Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rb Rc Rb Ra Rb Rb Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rc Rd Rc Rb Rc Rc Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd Rd Ra Rd Rc Rd Rd J J J K K K Ra Ra Ra D D D Comment Pop Stack Push PC Continue Pop Stack; Use AR for Address Push PC; Jump to Address in AR Jump to Address in AR Jump to Address in STK0; Pop Stack Jump to Address in STK0; Push PC Jump to Address in STK0 Pop Stack; Jump to Address on D Jump to Address on D; Push PC Jump to Address on D Principal Use End Loop Set-up Loop Continue End Loop JSR AR JMP AR RTS
Stack Ref (Loop) End Loop JSR D JMP D
1 = High, 0 = Low, X = Irrelevant, Assume Cn = High Note: STK0 is the location addressed by the stack pointer Table 2: Output and Internal Next-Cycle Register States for 2909/2911 Table 3 (Page 5) illustrates the execution of a subroutine using the 2909. The configuration of Figure 2 is assumed. The instruction being executed at any given time is the one contained in the microword register (WR). The contents of the WR also control (indirectly, perhaps) the four signals S0, S1, FE, and PUP. The starting address of the subroutine is applied to the D inputs of the 2909 at the appropriate time. In the column on the left is the sequence of microinstructions to be executed. At address J+2, the sequence control portion of the microinstruction contains the command "Jump to subroutine at A". At the time T2, this instruction is in the WR, and the 2909 inputs are set-up to execute the jump and save the return address. The subroutine address A is applied to the D inputs from the WR and appears on the Y outputs. The first instruction of the subroutine, I(A), is accessed and is at the inputs of the WR. On the next clock transition, l(A) is loaded into the WR for execution, and the return address J + 3 is pushed on to the stack. The return instruction is executed at T5. Table 4 is a similar timing chart showing one subroutine linking to a second, the latter consisting of only one microinstruction.
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MA2909/11
Execute Cycle S1, S0 FE PUP D PC STK0 STK1 STK2 STK3 Y (Y) WR T0 T1 T2 3 L H A J+3 A I(A) JSR A T3 0 H X X A+1 J+3 A+1 I(A + 1) I(A) T4 0 H X X A+2 J+3 A+2 RTS I(A + 1) T5 2 L L X A+3 J+3 J+3 I(J + 3) RTS T6 T7 T8 T9
2909 inputs (from WR)
Internal Registers 2909 Output ROM Output Contents of WR (instruction being executed)
0 0 H H X X X X J+1 J+2 J+1 J+2 I(J + 1) JSR A I(J) I(J + 1)
0 0 H H X X X X J+4 J+5 J+4 J+5 I(J + 4) I(J + 5) I(J + 3) I(J + 4)
Table 3: Subroutine Execution CONTROL MEMORY Microprogram Execute Cycle Address J-1 J J+1 J+2 J+3 J+4 A A+1 A+2 Sequencer Instruction JSR A I(A) RTS -
T0 T1 T2 T6 T7
T3 T4 T5
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MA2909/11
Execute Cycle S1, S0 FE PUP D PC STK0 STK1 STK2 STK3 Y (Y) WR T0 T1 T2 3 L H A J+3 A I(A) JSR A T3 0 H X X A+1 J+3 A+1 I(A + 1) I(A) T4 0 H X X A+2 J+3 A+2 JSR B I(A + 1) T5 2 L L X A+3 J+3 B RTS JRS B T6 0 H X X B+1 A+3 J+3 A+ 3 I(A + 3) RTS T7 0 H X X A+4 J+3 A+4 RTS I(A + 3) T8 2 L L X A+5 J+3 J+3 I(J + 3) RTS T9 0 H X X J+4 J+4 I(J + 4) I(J + 3)
2909 inputs (from WR)
Internal Registers 2909 Output ROM Output Contents of WR (instruction being executed)
0 0 H H X X X X J+1 J+2 J+1 J+2 I(J + 1) JSR A I(J) I(J + 1)
Table 4: Two Nested Subroutines CONTROL MEMORY Microprogram Execute Cycle Address J-1 J J+1 J+2 J+3 A A+1 A+2 A+3 A+4 B Sequencer Instruction JSR A JSR B RTS RTS -
T0 T1 T2 T9
T3 T4 T5 T7 T8
T6
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MA2909/11
DC CHARACTERISTICS AND RATINGS
Parameter Supply Voltage Input Voltage Current Through Any Pin Operating Temperature Storage Temperature Min -0.5 -0.3 -55 -65 Max 7 VDD+0.3 20 125 150 Units V V mA C C Note: Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions, or at any other condition above those indicated in the operations section of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 5: Absolute Maximum Ratings
Subgroup 1 2 3 7 8a 8b 9 10 11
Definition Static characteristics specified in Table 7 at +25C Static characteristics specified in Table 7 at +125C Static characteristics specified in Table 7 at -55C Functional characteristics at +25C Functional characteristics at +125C Functional characteristics at -55C Switching characteristics specified in Tables 8, 9 and 10 at +25C Switching characteristics specified in Tables 8, 9 and 10 at +125C Switching characteristics specified in Tables 8, 9 and 10 at -55C Table 6: Definition of Subgroups
Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL IDD
Parameter Output high voltage Output low voltage Input high level (Note 1) Input low level (Note 1) Input high current Input low current Tristate high current Tristate low current Power supply current
Conditions VDD = Min., IOH = -2.6mA, VIN = VIH or VIL VDD = Max., IOL = 16 mA, VIN = VIH or VIL Guaranteed input logical high voltage for all inputs Guaranteed input logical low voltage for all inputs VIN = VDD (Note 3) VIN = VSS (Note 3) VO = VDD (Note 3) VO = VSS (Note 3)
Min. VDD -0.5 VDD/2 -
Max. 0.5 0.8 10 -10 50 -50 10
Units V V V V A A A A mA
NOTES: Mil-Std-883, Method 5005, Subgroups 1, 2, 3. 1. These input levels provide no guaranteed noise immunity and should only be static tested in a noise-free environment. 2. VDD = 5V 10%, over full operating temperature range. 3. Guaranteed but not tested at low temperatures. Table 7: DC Operating Characteristics
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MA2909/11
Time Minimum clock low time Minimum clock high time
15 15
Table 8: Cycle Time and Clock Charcteristics
From input D1 S0, S1 ORI Cn ZERO OE LOW (enable) (Note 2) OE HIGH (disable) (Note 3) Clock: S1S0 = LH Clock: S1S0 = LL Clock: S1S0 = HL
Y 35 30 20 35 25 25 40 40 50
Cn + 4 40 35 30 25 40 45 45 45
From input RE RI PUP FE Cn DI ORI S0, S1 ZERO
Set-up time 10 10 20 20 15 20 20 20 25
Hold Time 10 7 5 10 5 0 0 0 0
Table 10: Guaranteed Set-up and Hold Times (all in ns) All times in ns across full voltage and temperature range. MIL-STD-883, method 5005, subgroups 9, 10 and 11.
Notes: 1. CL < 50pF 2. RL 680 3. RL 680, measured 0.5V change in output level Table 9: Maximum Combinational Propogation Delays
Figure 2
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MA2909/11
PACKAGE OUTLINES
Ref A A1 b c D e e1 H Me Z W Millimetres Min. 0.38 0.35 0.20 4.71 Nom. 2.54 Typ. 15.24 Typ. Max. 5.715 1.53 0.59 0.36 36.02 5.38 15.90 1.27 1.53 Min. 0.015 0.014 0.008 0.185 Inches Nom. 0.100 Typ. 0.600 Typ. Max. 0.225 0.060 0.023 0.014 1.418 0.212 0.626 0.050 0.060
XG404
REN R3 R2 R1 R0 OR3
1 2 3 4 5 6 7 8 9 Top View
28 VCC 27 CP 26 PUP 25 FEN 24 Cn+4 23 Cn 22 OEN 21 Y3 20 Y2 19 Y1 18 Y0 17 S1 16 S0 15 ZERON
D
D3 OR2 D2
14
1
OR1 10 D1 11 OR0 12 D0 13
15
28
GND 14
W Seating Plane ME
A1 A
H e b Z 15
C e1
Figure 3: 28-Lead Ceramic DIL (Solder Seal) - Package Style C
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MA2909/11
Ref A b c D E E2 e L Q S
Millimetres Min. 0.381 0.076 18.08 12.50 9.45 1.143 8.00 0.66 Nom. Max. 2.97 0.482 0.152 18.49 12.9 9.85 1.40 9.27 1.14 Min. 0.015 0.003 0.712 0.492 0.372 0.045 0.315 0.026 -
Inches Nom. Max. 0.117 0.019 0.006 0.728 0.508 0.388 0.055 0.365 0.045
XG543
E b
D S
e L A c
E2
Q
Pin 1
Figure 3: 28-Lead Dual Flatpack (Solder Seal) - Package Style C
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MA2909/11
RADIATION TOLERANCE
Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. GEC Plessey Semiconductors can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up 3x105 Rad(Si) 5x1010 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 1x10-10 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Table 11: Radiation Hardness Parameters
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance S R Q Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed
MAx2909xxxxx MAx2911xxxxx
QA/QCI Process (See Section 9 Part 4)
Package Type C N F Ceramic DIL (Solder Seal) Naked Die Flatpack (Solder Seal)
Test Process (See Section 9 Part 3)
Assembly Process (See Section 9 Part 2)
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see `Manufacturing Capability and Quality Assurance Standards' Section 9.
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MA2909/11
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire, SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017, 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576
* FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07 * GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55 * ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 * JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 * NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023 * SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 * SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 * TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260 * UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK
Tel: (01793) 518527/518566 Fax: (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. (c) GEC Plessey Semiconductors 1995 Publication No. DS3577-3.3 March 1995 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.
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